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HT93LC46 CMOS 1K 3-Wire Serial EEPROM
Features
* Operating voltage: - 2.2V~5.5V for temperature 0C to +70C - 2.4V~5.5V for temperature -40C to +85C - Operating: 5mA max. - Standby: 10mA max. * User selectable internal organization - 1K(HT93LC46): 1288 or 6416 * 3-wire Serial Interface * Write cycle time: 5ms max. * Automatic erase-before-write operation * Word/chip erase and write operation * Write operation with built-in timer * Software controlled write protection * 40-year data retention * 106 rewrite cycles per word * Industrial temperature range (-40C to +85C) * 8-pin DIP/SOP/TSSOP package
* Low power consumption
General Description
The HT93LC46 is a 1K-bit low voltage nonvolatile, serial electrically erasable programmable read only memory device using the CMOS floating gate process. Its 1024 bits of memory are organized into 64 words of 16 bits each when the ORG pin is connected to VCC or organized into 128 words of 8 bits each when it is tied to VSS. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. By popular microcontroller, the versatile serial interface including chip select (CS), serial clock (SK), data input (DI) and data output (DO) can be easily controlled.
Block Diagram
A d d re s s R e g is te r VCC A d d re s s D ecoder VSS M e m o r y C e ll A rra y 1 K : (1 2 8 8 o r 6 4 1 6 )
CS SK ORG
C o n tro l L o g ic and C lo c k G e n e ra te r
DI D a ta R e g is te r
O u tp u t B u ffe r
DO
Pin Assignment
CS 1 8 2 7 3 6 4 5 SK DI DO VCC NC ORG VSS NC VCC CS SK 4 5 H T93LC 46 8 S O P -B 3 6 2 7 1 8 ORG VSS DO DI
H T93LC 46 8 D IP -A /S O P -A /T S S O P -A
Rev. 1.90
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HT93LC46
Pin Description
Pin Name CS SK DI DO VSS I/O I I I O 3/4 Chip select input Serial clock input Serial data input Serial data output Negative power supply, ground Internal Organization When ORG is connected to VDD or ORG is floated, the (16) memory organization is selected. When ORG is tied to VSS, the (8) memory organization is selected. There is an internal pull-up resistor on the ORG pin. No connection Positive power supply Description
ORG
I
NC VCC
3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage.............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VCC 3/4 5V 5V Conditions 0C to +70C -40C to +85C DO unload, SK=1MHz DO unload, SK=1MHz Min. 2.2 2.4 3/4 3/4 3/4 3/4 0 0 0 0 2 0.9VCC 3/4 3/4 2.4 VCC-0.2 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 5.5 5 5 5 10 1 1 0.8 0.1VCC VCC VCC 0.4 0.2 3/4 3/4 5 5 Unit V V mA mA mA mA mA mA V V V V V V V V pF pF
VCC ICC1 ICC2 ISTB ILI ILO VIL
Operating Voltage Operating Current (TTL) Operating Current (CMOS) Standby Current (CMOS) Input Leakage Current Output Leakage Current Input Low Voltage
2.2~5.5V DO unload, SK=250kHz 5V 5V 5V 5V 2.2~5.5V 5V 2.2~5.5V 5V IOL=2.1mA CS=SK=DI=0V VIN=VSS~VCC VOUT=VSS~VCC, CS=0V 3/4 3/4 3/4 3/4
VIH
Input High Voltage
VOL
Output Low Voltage
2.2~5.5V IOL=10mA 5V IOH=-400mA VIN=0V, f=250kHz VOUT=0V, f=250kHz
VOH CIN COUT
Output High Voltage Input Capacitance Output Capacitance
2.2~5.5V IOH=-10mA 3/4 3/4
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HT93LC46
A.C. Characteristics
Symbol fSK tSKH tSKL tCSS tCSH tCDS tDIS tDIH tPD1 tPD0 tSV tHZ tPR Parameter Clock Frequency SK High Time SK Low Time CS Setup Time CS Hold Time CS Deselect Time DI Setup Time DI Hold Time DO Delay to 1 DO Delay to 0 Status Valid Time DO Disable Time Write Cycle Time VCC=5V10% Min. 0 250 250 50 0 250 100 100 3/4 3/4 3/4 3/4 3/4 Max. 2000 3/4 3/4 3/4 3/4 3/4 3/4 3/4 250 250 250 100 5 VCC=3V10% Min. 0 500 500 100 0 250 150 150 3/4 3/4 3/4 3/4 3/4 Max. 1000 3/4 3/4 3/4 3/4 3/4 3/4 3/4 500 500 250 200 5 VCC=2.2V Min. 0 1000 1000 100 0 500 200 200 3/4 3/4 3/4 3/4 3/4 Max. 500 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1000 1000 250 400 5 kHz ns ns ns ns ns ns ns ns ns ns ns ms Unit
A.C. Test Conditions Input rise and fall time: 5ns (1V to 2V) Input and output timing reference levels: 1.5V Output load: See Figure right
DO 100pF* 800W V C C = 1 .9 5 2 V
* ln c lu d in g s c o p e a n d jig
Output Load Circuit
CS
tC
SS
tC tS
KH
DS
tS
KL
SK
tC
SH
tD
IS
DI
t D IH V a lid D a ta tP
D0
V a lid D a ta tP
D1
DO
H i- Z
Rev. 1.90
3
July 9, 2009
HT93LC46
Functional Description
The HT93LC46 is accessed via a three-wire serial communication interface. The device is arranged into 64 words by 16 bits or 128 words by 8 bits depending whether the ORG pin is connected to VCC or VSS. The HT93LC46 contains seven instructions: READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL. When the user selectable internal organization is arranged into 6416 (1288), these instructions are all made up of 9(10) bits data: 1 start bit, 2 op code bits and 6(7) address bits. By using the control signal CS, SK and data input signal DI, these instructions can be given to the HT93LC46. These serial instruction data presented at the DI input will be written into the device at the rising edge of SK. During the READ cycle, DO pin acts as the data output and during the WRITE or ERASE cycle, DO pin indicates the BUSY/READY status. When the DO pin is active for read data or as a BUSY/READY indicator the CS pin must be high; otherwise DO pin will be in a high-impedance state. For successful instructions, CS must be low once after the instruction is sent. After power on, the device is by default in the EWDS state. And, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. The following are the functional descriptions and timing diagrams of all seven instructions. READ The READ instruction will stream out data at a specified address on the DO pin. The data on DO pin changes during the low-to-high edge of SK signal. The 8 bits or 16 bits data stream is preceded by a logical 0 dummy bit. Irrespective of the condition of the EWEN or EWDS instruction, the READ command is always valid and independent of these two instructions. After the data word has been read the internal address will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data. The address will wrap around with CS High until CS returns to LOW. EWEN/EWDS The EWEN/EWDS instruction will enable or disable the programming capabilities. At both the power on and power off state the device automatically entered the disable mode. Before a WRITE, ERASE, WRAL or ERAL instruction is given, the programming enable instruction EWEN must be issued, otherwise the ERASE/WRITE instruction is invalid. After the EWEN instruction is issued, the programming enable condition remains until power is turned off or a EWDS instruction is given. No data can be written into the device in the programming disabled state. By so doing, the internal memory data can be protected. WRAL The WRAL instruction writes data into the entire 6416 or 1288 memory cells in the programming enable mode. After the write-all instruction set has been issued, the data writing is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signals for the write-all operation, so the SK clock is not required. During the internal write-all operation, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over the DO pin will return to high and further instruction can be executed. ERASE The ERASE instruction erases data at the specified addresses in the programming enable mode. After the ERASE op-code and the specified address have been issued, the data erase is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signals for the internal erase, so the SK clock is not required. During the internal erase, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instructions can be executed. WRITE The WRITE instruction writes data into the device at the specified addresses in the programming enable mode. After the WRITE op-code and the specified address and data have been issued, the data writing is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signal for the internal writing, so the SK clock is not required. The auto-timing write cycle includes an automatic erase-before-write capability. So, it is not necessary to erase data before the WRITE instruction. During the internal writing, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instructions can be executed. ERAL The ERAL instruction erases the entire 6416 or 1288 memory cells to logical 1 state in the programming enable mode. After the erase-all instruction set has been issued, the data erase feature is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signal for the erase-all operation, so the SK clock is not required. During the internal erase-all operation, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instruction can be executed.
Rev. 1.90
4
July 9, 2009
HT93LC46
Timing Diagrams
READ
tC CS
DS
SK (1 ) 1 S ta r t b it 0 AN A0 tH
Z
DI
DO
H ig h - Z 0
DX
D0 *
DX
H ig h - Z
* A d d r e s s p o in te r a u to m a tic a lly c y c le s to th e n e x t w o r d
M ode AN DX
(X 1 6 ) A5 D15
(X 8 ) A6 D7
EWEN/EWDS
CS S ta n d b y
SK 0 (1 ) S ta r t b it 0 11=EW EN 00=EW DS
DI
WRITE
tC
DS
CS
v e r ify
S ta n d b y
SK 0 (1 ) S ta r t b it 1 AN
A N -1 A N -2
DI
A1
A0
DX
D0 tS
V
tH
Z
DO
H ig h - Z tP
R
busy
re a d y
ERASE
tC
DS
CS
v e r ify
S ta n d b y
SK 1 (1 ) S ta r t b it 1 AN
A N -1 A N -2
DI
A1
A0 tS
V
tH
Z
DO
H ig h - Z tP
R
busy
re a d y
Rev. 1.90
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July 9, 2009
HT93LC46
ERAL
tC
CS
DS
v e r ify
S ta n d b y
SK 0 (1 ) S ta r t b it 0 1 0 tS
V
DI
tH
Z
DO
H ig h - Z tP
R
busy
re a d y
WRAL
CS
tC
DS
v e r ify
S ta n d b y
SK 0 (1 ) S ta r t b it 0 0 1 H ig h - Z tP
R
DI
DX
D0 tS
V
tH
Z
DO
busy
re a d y
Instruction Set Summary
HT93LC46 Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Comments Read data Erase data Write data Erase/Write Enable Erase/Write Disable Erase All Write All Start bit 1 1 1 1 1 1 1 Op Code 10 11 01 00 00 00 00 Address ORG=0 ORG=1 X8 X16 A6~A0 A6~A0 A6~A0 A5~A0 A5~A0 A5~A0 Data ORG=0 ORG=1 X8 X16 D7~D0 D15~D0 3/4 D7~D0 D15~D0 3/4 3/4 3/4 D7~D0 D15~D0
11XXXXX 11XXXX 00XXXXX 00XXXX 10XXXXX 10XXXX 01XXXXX 01XXXX
Note: X stands for dont care Data should be written to the EEPROM in the format (8-bit or 16-bit mode) in which it is to be read.
Rev. 1.90
6
July 9, 2009
HT93LC46
Package Information
8-pin DIP (300mil) Outline Dimensions
A B
1 4 8 5
H C D E F G I
Symbol A B C D E F G H I
Dimensions in mil Min. 355 240 125 125 16 50 3/4 295 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 Max. 375 260 135 145 20 70 3/4 315 375
Rev. 1.90
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July 9, 2009
HT93LC46
8-pin SOP (150mil) Outline Dimensions
A 1
8
5 B 4
C
C' G D E F
H
a
* MS-012
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 150 12 188 3/4 3/4 4 16 7 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 50 10 8
Rev. 1.90
8
July 9, 2009
HT93LC46
8-pin TSSOP Outline Dimensions
8
5 E1
1
4
D A e R 0 .1 0 B y (4 C O R N E R S ) A1 A2 C L
E
L1
q
Symbol A A1 A2 B C D E E1 e L L1 y q
Dimensions in mm Min. 1.05 0.05 0.95 3/4 0.11 2.90 6.20 4.30 3/4 0.50 0.90 3/4 0 Nom. 3/4 3/4 3/4 0.25 3/4 3/4 3/4 3/4 0.65 3/4 3/4 3/4 3/4 Max. 1.20 0.15 1.05 3/4 0.15 3.10 6.60 4.50 3/4 0.70 1.10 0.10 8
Rev. 1.90
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July 9, 2009
HT93LC46
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 8N, TSSOP 8L Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0+0.5/-0.2 2.00.5 12.8+0.3/-0.2 18.20.2
Rev. 1.90
10
July 9, 2009
HT93LC46
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C TSSOP 8L Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 12.0+0.3/-0.1 8.00.1 1.750.10 5.50.5 1.5+0.1/-0.0 1.5+0.1/-0.0 4.00.1 2.00.1 7.00.1 3.60.1 1.60.1 0.3000.013 9.30.1 Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 12.0+0.3/-0.1 8.00.1 1.750.1 5.50.1 1.550.10 1.50+0.25 4.00.1 2.00.1 6.40.1 5.20.1 2.10.1 0.300.05 9.30.1
Rev. 1.90
11
July 9, 2009
HT93LC46
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.90
12
July 9, 2009

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